1. Field of the Invention
The present invention relates to a wafer level chip scale package and a manufacturing method for the same.
2. Description of the Related Art
A general tendency of technical development in an electronic industrial field is to reduce a size of an element. In a field of a semiconductor package, it is important to reduce a size of the semiconductor package identical to a size of a semiconductor die.
Recently, the semiconductor package is fabricated from a wafer through Re-Distribution Layer (RDL) and Under Bumped Metal (UBM) techniques. According to the RDL technique, wirings are induced from a plurality of bond pads formed on a semiconductor die to a large-sized pad aligned in a position different from positions of the bonding pads. In addition, UBM means an alloy allowing a solder ball to be easily welded on a large-sized pad. A package fabricated through the above RDL and UBM technique is called “Wafer Level Chip Scale Package (WLCSP)”.
The RDL and UBM techniques mainly include a sputtering technique and a plating technique.
According to the sputtering technique, the RDL can be used as the UBM. The sputtering technique is adaptable for fabricating a simple layered structure in a simple manufacturing process. That is, the sputtering technique includes insulative layer coating, align, develop and cure; RDL sputtering; PR coating, align and develop; etching; PR strip; leakage descum; insulative layer coating, align, develop and cure; flux printing; ball drop; reflow processes. Herein, the RDL (or UBM) consists of three layers in which a first layer is an adhesive layer, such as an aluminum layer or a titanium layer, a second layer is a diffusion layer including nickel-vanadium, and a third layer is a solder wetting layer including copper.
However, such a sputtering technique presents a problem in that interfacial bonding strength between copper and the insulative layer is weak. In addition, the sputtering technique represents weak wet-proof and corrosion-proof characteristics due to corrosion of copper. Since copper forms a strong intermetallic compound when it reacts with tin, which is a main component for a solder or a lead-free solder, reliability of the sputtering technique may be lowered.
In order to solve the above problem, a plating technique has been developed. However, the plating technique causes complicated manufacturing processes. That is, the plating technique includes insulative layer coating, align, develop and cure; seed layer sputtering; plating template coating, align and develop; RDL plating; plating template strip; seed layer etching; leakage descum; insulative layer coating, align, develop and cure; seed layer sputtering; plating template coating, align and develop; UBM plating; plating template strip; seed layer etching; leakage descum; flux printing; ball drop; reflow processes. Thus, the plating technique must repeat the seed layer sputtering process and the leakage descum process twice, so that the manufacturing processes are complicated. Herein, the seed layer is formed so as to plate the RDL or UBM. The seed layer is obtained through a sputtering process by using Ti/Cu. The RDL mainly includes Cu having superior electric conductivity, the UBM includes Ni corresponding to a lead-free solder, and a Cu layer is formed on a surface of Ni so as to prevent Ni from being oxidized. Thus, according to the plating technique, although the solder (or lead-free solder) includes a great amount of tin, Ni does not form the strong intermetallic compound, so reliability of the plating technique may be improved. However, as described above, the plating technique causes the complicated processes and must repeat the seed layer sputtering process and the leakage descum process twice, so a manufacturing process may be erroneously missed or unnecessarily added.